As computer and other digital systems become more complex and more capable, methods and hardware to enhance the transfer of data between system components or elements continually evolve. Data to be transferred include signals representing data, commands, or any other signals. System components or elements can include different functional hardware blocks on a single integrated circuit (IC), or on different ICs. The different ICs may or may not be on the same printed circuit board (PCB). System components typically include an input/output (I/O) interface specifically designed to receive data from other system components and to transmit data to other system components.
One consistent trend as computing systems become more capable is an increase in the amount of data to be transferred per time period. Some applications that require high data rates include game consoles, high definition television (HDTV), personal computer (PC) main memory, graphics processors, and various consumer devices not already mentioned. In response to the demand for increased data rates, double data rate (DDR) standards have been developed to standardize the behavior of hardware and software using high data rates. Several generations of graphics DDR (GDDR) standards have been developed specifically for graphics processing and video processing, which typically demand the capability to transfer and process very large amounts of data.
In some instances, conventional methods for handling well-known digital data transfer issues become impractical or unworkable as data rates become higher. For example, it is known that digital data transmission experiences errors. That is, signals will be incorrectly interpreted as having an incorrect binary value for a variety of reasons. Errors are quantified as an error rate, which can be a number of errors per unit time, or a number of errors per some number of transmissions. In response to this fact of digital data transmission, schemes for error detection and/or correction were developed. One common approach is error checking and correction (ECC), which is a collection of methods to detect errors in transmitted or stored data, and to correct them. This is done in many ways, all of them involving some form of coding. The simplest form of error detection is a single added parity bit or a cyclic redundancy check. Multiple parity bits cannot only detect that an error has occurred, but also which bits have been inverted, and should therefore be re-inverted to restore the original data. The more extra bits are added, the greater the chance that multiple errors will be detectable and correctable.
Conventional methods such as ECC are not practical for DDR interfaces. One reason is that in many DDR applications, the most likely errors are multi-bit errors (affecting more than one bit in a word) that are due to noise or timing issues. ECC is not well adapted to detect and correct such multi-bit errors.
Another reason conventional methods such as ECC are not practical for DDR interfaces is that ECC requires extra pins for parity bits. Additional pins for error detection may also be multiplied further when one system component, such as a processor, must interface with many other components, necessitating error detection and correction for each data path. Probably without exception, it is desirable to maintain as low a pin count as possible in modern mass-produced systems. Therefore, adding pins to handle errors is not a good solution, especially when even more pins may be required in high data rate systems (as compared to lower data rate systems) to provide acceptable error detection and correction.
Another approach to error detection according to various communication standards includes sending a signature with data from the sender to the receiver. The receiver compares the signature with the correct signature, and if there is an error, the sender is asked to retry. This method has disadvantages for many common high data rate applications. For example, the time to perform the comparison and request a retry may be undesirably long. In addition, the method requires an amount of intelligence to be present on both the receiver and transmitter. In many high data rate applications, this is not the case. For example, many high speed memories include a minimum amount of intelligence and are controlled by memory controllers that handle as many logic functions as possible for one or more memories under control. Having memories with minimal intelligence, or logic on board, reduces memory cost (a significant portion of system cost) and increases interface flexibility.
Another way to reduce errors is to run the system at a slower data rate, but that harms the very performance that is usually a goal to be achieved by higher data rates.